In synchronous integrated circuits, the integrated circuit is clocked by an external clock signal and performs operations at predetermined times relative to the rising and falling edges of the applied clock signal. Examples of synchronous integrated circuits include synchronous memory devices such as synchronous dynamic random access memories (SDRAMs), synchronous static random access memories (SSRAMs), and packetized memories like SLDRAMs and RDRAMs, and include other types of integrated circuits as well, such as microprocessors. The timing of signals external to a synchronous memory device is determined by the external clock signal, and operations within the memory device typically are synchronized to external operations. For example, commands are placed on a command bus of the memory device in synchronism with the external clock signal, and the memory device latches these commands at the proper times to successfully capture the commands. To latch the applied commands, an internal clock signal is developed in response to the external clock signal, and is applied to latches contained in the memory device to thereby clock the commands into the latches. The internal clock signal and external clock are synchronized to ensure the internal clock signal clocks the latches at the proper times to successfully capture the commands. In the example of FIG. 1, “external” is used to refer to signals and operations outside of the memory device, and “internal” to refer to signals and operations within the memory device. However, as the reader will appreciate, the principles described in the present disclosure are broadly applicable to aligning data output to a clock signal, external signals to input signals, etc. The present disclosure is directed to synchronous memory devices. However, as the reader will appreciate, the principles described herein are applicable to other types of synchronous integrated circuits.
Internal circuitry in the memory device that generates the internal clock signal introduces some time delay, causing the internal clock signal to be phase shifted relative to the external clock signal. As long as the phase-shift is small, timing within the memory device can be synchronized to the external timing. To increase the rate at which commands can be applied and at which data can be transferred to and from the memory device, the frequency of the external clock signal is increased, and in modern synchronous memories the frequency is in excess of 100 MHz. As the frequency of the external clock signal increases, however, the time delay introduced by the internal circuitry becomes more significant. This is true because as the frequency of the external clock signal increases, the period of the signal decreases and thus even small delays introduced by the internal circuitry correspond to significant phase shifts between the internal and external clock signals. As a result, the commands applied to the memory device may no longer be valid by the time the internal clock signal clocks the latches.
To synchronize external and internal clock signals in modern synchronous memory devices, a number of different approaches have been considered and utilized, including delay-locked loops (DLLs), phased-locked loops (PLLs), and synchronous mirror delays (SMDs), as will be appreciated by those skilled in the art. As used herein, the term synchronized includes signals that are coincident and signals that have a desired delay relative to one another.
A DLL is a feedback circuit that operates to feed back a phase difference-related signal to control a delay line, until the timing of a first clock signal, e.g., the system clock, is advanced or delayed such that its rising edge is coincident (or “locked”) with the rising edge of a second clock signal, e.g., the memory internal clock.
FIG. 1 illustrates a block diagram of a DLL 100. The DLL 100 receives a reference clock (RefCLK) 112 as an input and generates an output clock (CLKOut) signal 114 at its output. The CLKOut signal 114 is in turn fed back as a feedback clock signal (ClkFB or FB Clock) 116. The reference clock 112 can be the external system clock serving the system processor(s) or a delayed, buffered version of it. The system clock 112 may be supplied to the DLL 110 via one or more clock buffers (not shown).
The delay line in the DLL 100 can include a coarse delay line 118 and a fine delay line 120. The RefCLK 112 may be supplied first to the course delay line 118 whose output is then fed into the fine delay line 120 to generate the ClkOut signal 114. The coarse delay line 118 may include a number of coarse delay stages (not shown) and may be designed to produce an output signal having phase variation from an input signal within a coarse delay stage, whereas the fine delay line 120 is designed to produce an output signal having a phase variation from the input signal which is smaller than the deviation provided by the coarse delay line 118. In other words, the coarse delay line 118 is designed to bring its output signal to a near phase lock condition, or phase delayed condition, whereas the fine delay line 120 is designed to perform “fine tuning” to achieve the signal locking condition. Thus, a dual delay line (coarse and fine) DLL or PLL can provide a wide lock range while at the same time still providing a tight lock within reasonable time parameters.
In operation, the clock output signal 114 is used to provide the internal clock (not shown) used, for example, by memory device (not shown) to perform data read/write operations on memory cells (not shown) and to transfer the data out of the memory device to the data requesting device, e.g., a processor. As can be seen from FIG. 1, the ClkOut signal 114 (and, hence FBClock 116) is generated using delay lines 118, 120, which introduce a specific delay into the input RefClk 112 to obtain the “lock” condition.
As noted the purpose of the DLL 110 is to align or lock the internal clock (not shown) used by, for example, a memory device to perform data read/write operations to the system's external clock (not shown). A delay monitor 122 monitors a delay time of the output clock 114 from the coarse and fine delay lines 118, 120 to DQ output and a delay time of clock input buffer. A phase detector (PD) 124 compares the relative timing of the edges of the system's external clock and the memory's internal clock by comparing the relative timing of their respective representative signals, e.g., the RefClk 112 which relates to the system clock, and the FBClock signal 116 which relates to the memory's internal clock, so as to establish the lock condition. The PD 124 may compare a phase difference between the RefClk 112 and the FBClock 116 (supplied via the delay monitor) and output appropriate shift signals SHL (shift left) signal 125 and SHR (shift right) signal 126 for adjusting the phase difference between the RefClk 112 and the FBClock 116. The delay monitor circuit 122 may function as a buffer or dummy delay circuit for the ClkOut signal 114 before the ClkOut signal 114 is fed into the phase detector 124 as the FBClock 116. The output of the delay monitor 122, i.e., the FBClock 116, may effectively represent the memory's internal clock, which may be provided to various circuit elements in a memory device through the clock driver and data output stages (not shown). Thus, the delay monitor 122 attempts to maintain the phase relationship between the RefClk 112 and the FBClock 116 as close as possible to the phase relationship that exists between the external system clock and the memory's internal clock.
The RefClk 112 and the FBClk 116 are fed as inputs into the phase detector 124 for phase comparison. The output of the PD 124, e.g., one of the SHL 125 and SHR 126 signals, controls the amount of delay imparted to the RefClk 112 by the delay lines 118, 120. The SHL125 and SHR 126 signals may determine whether the RefClk 112 should be shifted left (SHL) or shifted right (SHR) through the appropriate delay units in the delay lines 118, 120 so as to match the phases of the ReiCik 112 and the FBClock 116 to establish the lock condition. The SHL 125 and SHR 126 maybe supplied to the delay lines 118, 120 via shift register 128, which may control the delay time of the delay time of the delay lines 118, 120 according to the shift signals SHL and SHR from the phase detector 128. Based on the status of the SHL 125 and the SHR 126 signals input thereto, the shift register 128 may generate one or more delay adjustment signals 130 to carry out the left or right shift operations indicated by the phase detector 124. As is known in the art, a shift left operation in delay line results in adding a delay to the clock signal input thereto, whereas a shift right operation reduces the delay. The delay adjustment signals 130 essentially serve the same purpose as the SHL 125 or the SHR 126 signals, but their application to the coarse and fine delay lines 118, 120, respectively, is controlled by the shift register 128. The cumulative delay imparted to the RefClk 112 by the series-connected coarse and fine delay lines 118, 120, respectively, operates to adjust the time difference between the ClkOut signal 114 (as represented by FBClock 116) and the input RefClk 112 until they are aligned. The phase detector 124 generates the shift left (SHL) and shift right (SHR) signals depending on the detected phase difference or timing difference between the RefClk 112 and the FBClock 116, as is known in the art.
In the DLL 110 of FIG. 1, when the RefClk 112 is output from the coarse delay line 118 and input to the fine delay line 120, the switching at the boundary of coarse and fine delays may result in creation of jitters(s) or discontinuity in the final signal output from the fine delay line 120, i.e., the ClkOut signal 114. These clock perturbations may not be desirable, especially when an electronic device, e.g., a memory device is operated at significantly high clock frequencies, e.g., 800 MHz or higher. Furthermore, as reference clock frequencies increase, the DLL architecture in FIG. 1 may not be suitable to adequately control coarse shifting at such high frequencies, which may negatively affect the signal integrity of the ClkOut 114 and may also delay the establishment of a lock condition.
It is therefore desirable to devise a clock synchronization circuit that avoids output clock signal jitter at high frequencies and the also performs a smooth phase transition at the boundary of the coarse and fine delays. It is also desirable to have this synchronization circuit able to adequately control coarse shifting at higher clock frequencies without any limitations.